Intel Expands its Scalable System Framework with new Reference Architecture and Reference Designs
By   |  July 05, 2016

With the recently announced availability of Intel Scalable System Framework (Intel SSF) Architecture Specification and Reference Designs at ISC 2016, Intel is making it easier to fuel continuing advancements of human insight and discoveries through high-performance computing (HPC). Intel has talked at length about Intel SSF as its design approach to scalable, balanced HPC systems built on processors, fabrics, storage, and software specifically designed to work in concert to benefit users of HPC. The Reference Architectures (RAs) and Reference Designs take Intel SSF to the next step —deploying it in ways that will allow users to confidently run their workloads and allow system builders to innovate and differentiate designs based on Intel SSF.

The RA describes the high-level system architecture and application platform. A Reference Design is one verified implementation of a Reference Architecture. The design includes hardware and software Bill of Materials information and cluster configuration instructions that can be used “as is” or built on.

According to Andy Parma, Marketing Manager, Intel, “the Reference Architecture and Reference Designs aren’t simply concepts. They are documented, validated deployment examples based on industry best practices and conventions to give specific types of workloads, such as modeling and simulation, the high-performance resources they need for advanced computing. Intel has built and validated systems based on the reference designs.”

Over 30 companies have committed to Intel SSF, including leading system builders and ISVs, who will validate their products. Dozens more are expected to engage with Intel with the transition of the Intel Cluster Ready program partners to the Intel Scalable System Framework program by the end of this year.

“While the Reference Architectures, “added Parma, “define a system that at a minimum has a high-performance Intel processor and interconnect and validated HPC tools and software, it leaves room for the system builders to design to their customers’ requirements and to differentiate and innovate on their own. For example, Intel Enterprise Edition for Lustre* Software is part of Intel SSF, but some customers will have other file system requirements and thus will choose a different technology. Also, it gives builders the options to choose Intel SSDs or spinning hard drives, again, depending on customer needs and design requirements. So, there’s built-in flexibility, but also foundational requirements to make it a high-performance Intel SSF system.”

What these documents mean to the system builders is that they can work from a proven foundation of technologies to deliver high-performance solutions quickly and enhance and modify the design to meet customer needs. To the end user they mean faster time to insight with the knowledge that software from Intel partners will run on Intel SSF systems.

When speaking in support of Supermicro’s commitment to Intel SSF, Charles Wuischpard, Vice President of the Data Center Group and General Manager of Intel’s High Performance Computing Platform Group at Intel said, “Supermicro is poised to bring some of the most exciting HPC products to market using the Intel Scalable System Framework. Supermicro’s adoption of Intel’s latest technologies, including the new Intel Xeon Phi™ processor and Intel Omni-Path Architecture, will deliver remarkably deeper insights and innovations for research and commercial applications in science, analytics, and machine learning.”

The first RA announced at ISC and now available at intel.com/ssfconfigurations targets classic HPC clusters, used in both enterprise and research/academia, which support traditional modeling and simulation workloads. Two Reference Designs cover cluster builds, one based on Intel Xeon processor E5-2600 v4 family with Intel Omni-Path Architecture fabric and the other based on Intel Xeon processor E5-2600 v4 family with Intel Ethernet controllers. Both are based on the OpenHPC v1.1 software stack.

These documents are only the beginning of what will grow to additional RAs and validated Reference Designs based on the architectures. In the future, a family of Reference Architectures will span small clusters through scalable supercomputers, systems that require special capabilities not found in smaller configurations. RAs will be written that support cloud, data analytics, machine learning, and visualization workloads in addition to traditional HPC workloads.

“What’s important here is the compatibility of software across the architecture as solutions evolve,” commented Parma. “Users want to have a consistent framework that can run their many workloads without having to deploy an entirely different set of components. Intel SSF and the Reference Architectures give them that.”

Intel also announced at ISC the introduction of Intel HPC Orchestrator, an HPC software stack central to the Intel SSF approach and built on the OpenHPC community system software, hosted by the Linux Foundation. Intel HPC Orchestrator is a family of products ready for deployment on a Reference Design or other HPC cluster. It includes a configuration of pre-integrated, pre-tested, and pre-validated system-level software and tools with ongoing support by Intel. In addition to the OpenHPC software, it adds some proprietary Intel HPC tools, such as the Intel Parallel Studio XE Cluster Edition 2016 Suite. Intel HPC Orchestrator is designed to reduce the time required to ready an HPC solution for production, while providing Intel tools HPC developers can effectively leverage.

Intel is enabling greater democratization of HPC for a wider community of users. With Intel SSF and its RAs and Reference Designs, more HPC capabilities will become available to more people who can benefit from this level of computing—without them having to become HPC experts. As HPC deployments based on Intel SSF reach into the cloud, Cloud Service Providers will be able to open whole new territories for users with no HPC experience, allowing them to discover the value of parallel computing and become familiar with its capabilities before investing in their own systems.

Ken Strandberg is a technical story teller. He writes articles, white papers, seminars, web-based training, video and animation scripts, and technical marketing and interactive collateral for emerging technology companies, Fortune 100 enterprises, and multi-national corporations. Mr. Strandberg’s technology areas include Software, HPC, Industrial Technologies, Design Automation, Networking, Medical Technologies, Semiconductor, and Telecom. Mr. Strandberg can be reached at ken@catlowcommunications.com.

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