One year after the official announcement of Xeon Phi 1.0 (“Knight’s Corner”), Intel took advantage of the SuperComputing Conference to organize a round-table discussion about the future of its x86 accelerator. This was the occasion for the company to publicly state its long-term intentions and to remind the audience that the objective of Xeon Phi is to provide a non-disruptive transition path toward multicore and manycore architectures, i.e. to allow applications to be executed on an ever larger number of processors within the context of x86 conventional programming.

As developers know too well, the main problem of heterogeneous computing today is data loading onto the accelerators. Intel intends to provide a lasting solution with the forthcoming “Knight’s Landing” memory architecture: a cache mechanism located within the core itself, and in-package high bandwidth memory to be connected to large quantities of DDR4. The use of this cache to control memory placement and exploit the extra cores should allow Knight’s Landing – according to Intel engineers – to run applications natively rather than in accelerated mode, thus avoiding data transfers.

As a bonus, we now know more about the main specifications of Phi 2.0: manufactured in 14 nm technology and available in socket format, it will carry 72 Airmont (Intel Atom) cores with out-of-order 512-bit vector instructions (AVX-512), 8 to 16 GB of memory within the accelerator, 6 access channels to the future DDR4 memory (up to 384 GB @ 115 GB/s!) and 36 PCIe Gen3 lines. On the performance front, Intel announces 3 Tflops double precision, or 3X Knight’s Corner performance for a 160 to 200 W TDP. The card version will be limited to two channels of DDR4 for a maximum of 64 GB of RAM. An “F” version should also be available, with optical interconnects (the “F” is for Fabric) and a 15 W higher TDP. Regarding the release date, nothing has changed: depending on the version, you will need to wait until the middle or the end of 2015 to proudly say that you use one.