Both the frequency wall and Moore’s Law explain why, during the last decade, processor manufacturers have been constantly multiplying and parallelizing processor cores. The increase in transistors count and their miniaturization – along with efforts on the software side – have certainly boosted overall performance levels but the downside is the increasing pressure on the interconnect bus. In a context where 10+ cores are more and more common within a single processor, everybody agrees that we have moved beyond the bottleneck level and almost reached the breaking point. Each core having to guarantee the consistency of its cache, bus transactions are in effect exclusive, which can paralyze a core if it must wait to continue its task.

This is what led MIT researchers to revive the idea of connecting cores like computers on the Internet – a concept both simple and full of potential. Unlike a conventional bus, where every core can communicate directly with every other core, a network-on-a-chip (NoC) allows a core to communicate with its neighbors through an integrated router responsible for distributing queries. As on the Internet, if a path is blocked, alternative routes are available, which makes the entire “network” much more powerful, adaptive and resilient than the sum of its components.

If the idea seems promising – at least on paper – its feasibility has now to be demonstrated, especially in regard to cache consistency. With communications not reaching each and every cores, some cores may not be able to “snoop” the latest version of the data. The MIT team is working on this based on a prioritization scheme (details haven’t been published yet). They have announced they should soon validate a 36-core prototype running a forked Linux featuring additions dedicated to routing support. If everything goes as planned, the industry shouldn’t be long to adapt…