Intel unveils Knight's Landing a bit more
By   |  June 28, 2014

Although it can be used independently, that is, in native and non-accelerator mode, Xeon Phi’s memory dotation is too small to stand a full 61-core workload. That being said, on the road to exascale, compute power is not the key issue anymore. What matters is to feed the cores efficiently enough while minimizing data movement in order to optimize energy consumption.

Enter an innovative solution from Micron called “Hybrid Memory Cube” – a stacked memory design featuring a nominal performance increase of about 15x as well as 70% energy savings and 90% footprint reduction. We covered this in our French edition about a year ago and now, at ISC’14, Intel just announced a partnership with the memory maker in order to equip the next generation of Phi with this technology renamed “On-Package Memory” for the occasion.

According to project managers, who were not very talkative about technical details, the new version of Phi using Silvermont cores should offer more than 3 TFLOPS DP and integrate the Micron technology with 16GB on-board, 5x the DDR4 bandwidth, a reduced stacked space and a 5x increase in energy efficiency. The goal, clearly, is to bypass the host CPU as much as possible in order to avoid data movement on the PCI bus which, by the way, will also simplify programming.

 

Another interesting but even less detailed announcement at ISC was Intel’s new interconnect system – “Omni Scale Fabric”. The objective here is to replace TrueScale in both Xeon and Xeon Phi in order to break current memory and I/O limitations, which are beginning to constrain performance and scalability. This should result in a significant reduction in the number of active and passive components at accelerator and system levels, meaning improved density and energy efficiency. As with a number of Intel announcements this year, the release date for this new generation of Xeon / Xeon Phi should be around the third quarter of 2015. Now is the time to be patient…

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